RTL power modeling and estimation based on bit and word level switching properties

We introduce the concept and first results of a fast power estimation flow, based on RTL power macromodeling. It provides the capability to estimate power for complete processing steps of an algorithm using real data and considering the target hardware. For that, we developed an efficient power modeling technique for RTL combinational macroblocks based only on word and bit level switching information. These models reduce the estimation error compared to the Hamming-distance model at least by 64%, while the total average errors achieved over a wide range of test modules and input stimuli are about 5%. This approach has been extended to sequential RTL macroblocks. Solutions for handling the volume of data, acceleration of simulation and estimation accuracy are provided. In all, the flow enables a speed up of about 100 times compared to gate level estimation, even though having at least the same accuracy.