Retiming of latches for power reduction of DSP designs

S. Simon, C. V. Schimpfle, M. Wroblewski, J. A. Nossek

Publikation: Beitrag in FachzeitschriftKonferenzartikelBegutachtung

5 Zitate (Scopus)

Abstract

In this paper a retiming methodology is proposed which reduces the power consumption of digital CMOS circuits. The application of high level synthesis tools for arbitrary designs usually leads to the usage of edge triggered registers. However, VLSI implementations of DSP algorithms which are considered here make level sensitive registers applicable. Level sensitive registers consist of two latches which store the data for half a clock period. If these latches are placed separately in the circuit then glitching can be reduced and single latches can store data on the gate capacity of the logic instead of the gate of additional inverters. These two effects reduce the power dissipation of the total circuit and savings of the considered DSP implementation up to 20% or more have been achieved.

OriginalspracheEnglisch
Seiten (von - bis)2168-2171
Seitenumfang4
FachzeitschriftProceedings - IEEE International Symposium on Circuits and Systems
Jahrgang3
PublikationsstatusVeröffentlicht - 1997
VeranstaltungProceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97. Part 4 (of 4) - Hong Kong, Hong Kong
Dauer: 9 Juni 199712 Juni 1997

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