Resonant multistage charging of dominant capacitances

Christoph Saas, Josef A. Nossek

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

Abstract

It has been shown [2] that adiabatic switching can significantly reduce the dynamic power dissipation in an integrated circuit. Due to the overhead in the realization of adiabatic logic blocks [3] the best results are achieved when it is used only for charging dominant loads in an integrated circuit [7]. It has been demonstrated [4] that a multi stage driver is needed for minimal power dissipation. In this article a complete three stage driver including the generation of oscillating supply is described. To obtain a minimal power dissipation during synchronization the resonant frequency has to be constant. Therefore the waveforms for the logic states of the signal and the realization of a single stage differ from those presented in [4]. In the H-SPICE simulations losses of the inductor are taken into account. This allows to estimate the power reduction that is achievable in a real system.

OriginalspracheEnglisch
TitelIntegrated Circuit Design
UntertitelPower and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings
Redakteure/-innenBertrand Hochet, Antonio J. Acosta, Manuel J. Bellido
Herausgeber (Verlag)Springer Verlag
Seiten101-107
Seitenumfang7
ISBN (Print)9783540441434
DOIs
PublikationsstatusVeröffentlicht - 2002
Veranstaltung12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002 - Seville, Spanien
Dauer: 11 Sept. 200213 Sept. 2002

Publikationsreihe

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Band2451
ISSN (Print)0302-9743
ISSN (elektronisch)1611-3349

Konferenz

Konferenz12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002
Land/GebietSpanien
OrtSeville
Zeitraum11/09/0213/09/02

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