Reduced Multisource Switched-Capacitor Multilevel Inverter Topologies

Mohammad Ali Hosseinzadeh, Maryam Sarebanzadeh, Cristian F. Garcia, Ebrahim Babaei, Jose Rodriguez, Ralph Kennel

Publikation: Beitrag in FachzeitschriftArtikelBegutachtung

33 Zitate (Scopus)

Abstract

Multisource switched-capacitor multilevel inverters are proper topologies when multiple dc sources are available as renewable energy sources. However, these multilevel inverters have the main drawbacks of requiring a large number of power semiconductors and capacitors and a low boost factor to achieve a large number of voltage levels, which complicate control, reduce performance, and raise the cost. This article presents two configurations for multisource switched-capacitor multilevel inverters. First, a basic multisource switched-capacitor topology is proposed with a small number of capacitors and semiconductors that produce a zero voltage level and a large number of positive voltage levels. The input dc sources are operated in an asymmetric trinary algorithm, while the capacitors are charged/discharged in a binary algorithm using parallel/series modes (without the need for any circuit balancing). Based on the proposed basic topology, two multilevel inverter topologies are proposed, which create bipolar output voltage levels using two different circuits at the output. The first proposed topology uses a standard H-bridge inverter at the output of the basic topology, while the second topology uses an extra switched-capacitor (self-balancing) circuit. The comparison indicates that both the proposed topologies have advantages over most of the reported multisource switched-capacitor multilevel inverters, such as a small number of capacitors, a small number of power semiconductors, low voltage stress, and high boost factor. Furthermore, the proposed topologies decrease the low cost factor in comparison to other topologies. The capacitors' capacitance, power losses, and voltage ripple losses are all measured and evaluated in detail. Theoretical research is validated with the use of laboratory prototypes to validate the performance of the proposed topologies.

OriginalspracheEnglisch
Seiten (von - bis)14647-14666
Seitenumfang20
FachzeitschriftIEEE Transactions on Power Electronics
Jahrgang37
Ausgabenummer12
DOIs
PublikationsstatusVeröffentlicht - 1 Dez. 2022

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