Abstract
This paper presents a new technology that accelerates system verification. In a real life example, we achieved a speed-up of a factor of about 5000. The key for this speed-up is a configurable, synthesizable testbench architecture, which can be completely mapped to emulators or FPGAs. Exploiting generic controllers and re-using protocol-specific stimuli generators combined with topology and microprogram generation is responsible for almost zero overhead compared to behavioral testbenches.
Originalsprache | Englisch |
---|---|
Aufsatznummer | 1253741 |
Seiten (von - bis) | 1038-1043 |
Seitenumfang | 6 |
Fachzeitschrift | Proceedings -Design, Automation and Test in Europe, DATE |
DOIs | |
Publikationsstatus | Veröffentlicht - 2003 |
Extern publiziert | Ja |
Veranstaltung | Design, Automation and Test in Europe Conference and Exhibition, DATE 2003 - Munich, Deutschland Dauer: 3 März 2003 → 7 März 2003 |