Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement

T. Baumann, J. Berthold, T. Niedermeier, T. Schoenauer, J. Dienstuhl, D. Schmitt-Landsiedel, C. Pacha

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

4 Zitate (Scopus)

Abstract

Performance improvement of an ARM926 microprocessor core by selective replacement of standard master-slave flip flops using low-VT flip flops or a novel type of pulsed flip flop (P-FF) is investigated. Different replacement strategies are proposed that are independent of path and pipeline topologies. These strategies are compared to each other concerning performance improvement and costs. For an existing 90nm CMOS design a 5% speed improvement on design level is achieved at low area overhead of 1%. An experimental verification of the proposed concept using a loop of critical paths shows 12% speed increase at 500MHz and VDD=1.2V in a 65nm CMOS technology.

OriginalspracheEnglisch
TitelESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference
Seiten308-311
Seitenumfang4
DOIs
PublikationsstatusVeröffentlicht - 2007
VeranstaltungESSCIRC 2007 - 33rd European Solid-State Circuits Conference - Munich, Deutschland
Dauer: 11 Sept. 200713 Sept. 2007

Publikationsreihe

NameESSCIRC 2007 - Proceedings of the 33rd European Solid-State Circuits Conference

Konferenz

KonferenzESSCIRC 2007 - 33rd European Solid-State Circuits Conference
Land/GebietDeutschland
OrtMunich
Zeitraum11/09/0713/09/07

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