Pareto optimization of analog circuits considering variability

The trade-off between competing design objectives is often decided at the beginning of the analog sizing process by assigning weights to the design objectives. Architectural design, however, requires the knowledge of all possible optimal trade-offs of a building block. Methods for Pareto optimization provide the set of all optimal trade-offs, the so-called Pareto front. The next generation of analog Pareto optimization tools additionally has to consider the manufacturing variations. This paper describes an approach to this challenging problem. First, analog Pareto optimization will be developed as a set of specific nonlinear programming problems that provide a discretization of the Pareto front of competing performance features. Second, a general problem formulation to consider manufacturing variations and operating ranges of circuit parameters in analog Pareto optimization will be presented. Third, an efficient solution approach to the resulting tolerance Pareto optimization problem will be described. It is based on a combination of nominal Pareto optimization and realistic worst-case analysis on discrete Pareto points. It provides high efficiency at acceptable loss in accuracy.