Optimization of L_Gate for ggNMOS ESD protection devices fabricated on bulk- and SOI- substrates, using process and device simulation

Keyphrases

• Device Simulation 100%
• Process Simulation 100%
• Snapback 100%
• Grounded Gate NMOS (GGNMOS) 100%
• Bulk Substrate 100%
• ESD Protection Device 100%
• SOI Substrate 100%
• Doping Profile 50%
• High Current 50%
• CMOS Technology 50%
• Gate Length 50%
• Current Characteristics 50%
• Transport Parameters 50%
• Differential Resistance 50%
• Electro-thermal Simulation 50%
• Physical Transport 50%
• SOI Devices 50%
• Holding Voltage 50%

Engineering

• Simulation Result 100%
• Measured Data 100%
• Protection Device 100%
• Gate Length 100%
• Holding Voltage 100%

Earth and Planetary Sciences

• High Current 100%