Optimization of LGate for ggNMOS ESD protection devices fabricated on bulk- and SOI- substrates, using process and device simulation

A. I. Deckelmann, G. Wachutka

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

5 Zitate (Scopus)

Abstract

The high-current characteristics of ggNMOS fabricated on bulk- as well as on SOI-substrates using a 0.6 μm-CMOS technology have been simulated for different values of the gate length LGate. Prior to the simulation, the doping profiles and physical transport parameters were calibrated with reference to measured data. The snapback differential resistance Rspdiff is found to be higher for SOI-devices. Also, an optimum value of LGate is determined for the bulk-substrate, yielding a minimum snapback holding voltage VH. For SOI fabrication, however, VH decreases with shrinking LGate. We explain this behavior on the basis of the electrothermal simulation results.

OriginalspracheEnglisch
TitelSISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers Inc.
Seiten251-254
Seitenumfang4
ISBN (elektronisch)0780378261
DOIs
PublikationsstatusVeröffentlicht - 2003
Veranstaltung2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003 - Boston, USA/Vereinigte Staaten
Dauer: 3 Sept. 20035 Sept. 2003

Publikationsreihe

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Band2003-January

Konferenz

Konferenz2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003
Land/GebietUSA/Vereinigte Staaten
OrtBoston
Zeitraum3/09/035/09/03

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