TY - GEN
T1 - Optimization of Bit Mapping and Quantized Decoding for Off-the-Shelf Protograph LDPC Codes with Application to IEEE 802.3ca
AU - Steiner, Fabian
AU - Kramer, Gerhard
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/7/2
Y1 - 2018/7/2
N2 - Protograph-based, off-the-shelf low-density parity-check (LDPC) codes are optimized for higher-order modulation and quantized sum-product decoders. As an example, for the recently proposed LDPC code from the upcoming IEEE 802.3ca standard for passive optical networks (PONs), an optimized mapping of the bit channels originating from bit-metric decoding to the protograph variable nodes gains 0.4 dB and 0.3 dB at a bit-error rate of 10-6 for shaped and uniform signaling, respectively. Furthermore, the clipping value for a quantized sum-product LDPC decoder is optimized via discretized density evolution.
AB - Protograph-based, off-the-shelf low-density parity-check (LDPC) codes are optimized for higher-order modulation and quantized sum-product decoders. As an example, for the recently proposed LDPC code from the upcoming IEEE 802.3ca standard for passive optical networks (PONs), an optimized mapping of the bit channels originating from bit-metric decoding to the protograph variable nodes gains 0.4 dB and 0.3 dB at a bit-error rate of 10-6 for shaped and uniform signaling, respectively. Furthermore, the clipping value for a quantized sum-product LDPC decoder is optimized via discretized density evolution.
UR - http://www.scopus.com/inward/record.url?scp=85062410759&partnerID=8YFLogxK
U2 - 10.1109/ISTC.2018.8625335
DO - 10.1109/ISTC.2018.8625335
M3 - Conference contribution
AN - SCOPUS:85062410759
T3 - International Symposium on Turbo Codes and Iterative Information Processing, ISTC
BT - 2018 IEEE 10th International Symposium on Turbo Codes and Iterative Information Processing, ISTC 2018
PB - IEEE Computer Society
T2 - 10th IEEE International Symposium on Turbo Codes and Iterative Information Processing, ISTC 2018
Y2 - 3 December 2018 through 7 December 2018
ER -