TY - GEN
T1 - On the Critical Role of Ferroelectric Thickness for Negative Capacitance Transistor Optimization
AU - Prakash, Om
AU - Gupta, Aniket
AU - Pahwa, Girish
AU - Chauhan, Yogesh S.
AU - Amrouch, Hussam
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021/4/8
Y1 - 2021/4/8
N2 - This paper demonstrates the critical role that Ferroelectric (FE) layer thickness (t_{FE}) plays in Negative Capacitance (N C) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a 14nm FDSOI technology node, exploring the impact of t_{FE on the figures of merit of n-type and p-type devices, voltage transfer characteristic (VTC) and noise margin of inverter as well as the speed of buffer circuits. First, we analyze the device electrical parameters (e.g., I_{ON}, SS, I_{ON}/I_{OFF and C_{gg}) by varying t_{FE up to the maximum level at which hysteresis in the I- V characteristic starts. Then, we analyze the deleterious impact of Negative Differential Resistance (NDR), due to the drain to gate coupling, demonstrating how it imposes an additional constraint limiting the maximum t_{FE. We show the consequences of NDR effects on the VTC and noise margin of inverter, which are essential components for constructing robust clock trees in any chip. Finally, when it comes to circuit's performance, we demonstrate how the considerable increase in the gate's capacitance due to FE seriously degrades the circuit's performance imposing further constraints limiting the maximum t_{FE. All in all, our analysis provides guidance for device and circuit designers to select the optimal FE thickness for NCFETs in which hysteresis-free operations, reliability, and performance are jointly optimized.
AB - This paper demonstrates the critical role that Ferroelectric (FE) layer thickness (t_{FE}) plays in Negative Capacitance (N C) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a 14nm FDSOI technology node, exploring the impact of t_{FE on the figures of merit of n-type and p-type devices, voltage transfer characteristic (VTC) and noise margin of inverter as well as the speed of buffer circuits. First, we analyze the device electrical parameters (e.g., I_{ON}, SS, I_{ON}/I_{OFF and C_{gg}) by varying t_{FE up to the maximum level at which hysteresis in the I- V characteristic starts. Then, we analyze the deleterious impact of Negative Differential Resistance (NDR), due to the drain to gate coupling, demonstrating how it imposes an additional constraint limiting the maximum t_{FE. We show the consequences of NDR effects on the VTC and noise margin of inverter, which are essential components for constructing robust clock trees in any chip. Finally, when it comes to circuit's performance, we demonstrate how the considerable increase in the gate's capacitance due to FE seriously degrades the circuit's performance imposing further constraints limiting the maximum t_{FE. All in all, our analysis provides guidance for device and circuit designers to select the optimal FE thickness for NCFETs in which hysteresis-free operations, reliability, and performance are jointly optimized.
UR - https://www.scopus.com/pages/publications/85106495476
U2 - 10.1109/EDTM50988.2021.9420894
DO - 10.1109/EDTM50988.2021.9420894
M3 - Conference contribution
AN - SCOPUS:85106495476
T3 - 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
BT - 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
Y2 - 8 April 2021 through 11 April 2021
ER -