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MaskVer: A tool helping designers detect flawed masking implementations

  • Technische Universität München

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

2 Zitate (Scopus)

Abstract

Hardening cryptographic algorithms against sidechannel attacks is a complex but crucial task in today's hardware implementations. One of the most promising countermeasures is Boolean Masking. Designers spend much effort to optimise and customise their masking schemes, but many proposed masked implementations were eventually broken, because they are somehow flawed-not necessarily restricted to a specific error, but to an overall leakage problem. As today's EDA tools hardly support masking, the masking process is still a manual task for the designer. Even worse, due to the lack of capable EDA tools, after synthesis there is no guarantee that the masking still applies and is not optimised. Checking each and every gate of a netlist for masking flaws after synthesis is a time consuming, expensive, and infeasible task. In this paper, we propose a graph based method to reduce the number of gates to be checked. We also present a prototype implementation of our tool to help designers detecting flawed masking in their designs.

OriginalspracheEnglisch
Titel2016 1st IEEE International Verification and Security Workshop, IVSW 2016
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers Inc.
Seiten25-30
Seitenumfang6
ISBN (elektronisch)9781509011414
DOIs
PublikationsstatusVeröffentlicht - 13 Sept. 2016
Veranstaltung1st IEEE International Verification and Security Workshop, IVSW 2016 - Sant Feliu de Guixols, Spanien
Dauer: 4 Juli 20166 Juli 2016

Publikationsreihe

Name2016 1st IEEE International Verification and Security Workshop, IVSW 2016

Konferenz

Konferenz1st IEEE International Verification and Security Workshop, IVSW 2016
Land/GebietSpanien
OrtSant Feliu de Guixols
Zeitraum4/07/166/07/16

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