Iterative FPGA implementation easing safety certification for mixed-criticality embedded real-time systems

The design and operation of an aircraft, a railway, and a nuclear power station that include either safety-critical or safety-related systems require a proof that its safety is assured. The process providing this proof is called certification. This paper suggests an iterative FPGA implementation and iterative certification concept for FPGA-based systems to provide design-time adaptability while the complexity is still kept low to ease certification. The practical evaluation of this concept demonstrates that reuse at implementation level of a previously implemented part is to 100% usable for iterative certification. Regarding the resource utilization and complexity, the evaluation shows that there are potential savings in resource utilization and complexity compared to conventional run-time configurable designs. Iterative certification reduces the recertification of a whole design to a recertification of the changed part only and a verification tool qualification. It is shown that tool qualification can be accomplished with relatively moderate effort. Therefore, the presented concept substantially eases the certification process when using modular design and building block reuse.