In situ measurement of aging-induced performance degradation in digital circuits

This paper presents a novel approach to evaluate the impact of aging mechanisms of digital circuits over their lifetimes, focusing on the analysis of measurement data. Aging of devices results in a performance reduction of digital circuits, which might result in timing violations and thus functional failure. To be able to evaluate the current timing behavior of circuits, their timing properties can be observed by in situ timing monitors. In this work, the timing slack of functional paths is extracted by in situ monitors and measured by a 5-bit time to digital converter (TDC) to accurately assess the reliability status of the circuit. Thus, aging induced performance degradation over lifetime can be monitored. By observing the timing properties of functional paths, intra-die variations of process, voltage, temperature and aging (PVTA) are monitored [1, 2]. Thus, an accurate assessment of the reliability status of the circuit is achieved.