Improving verification coverage of analog circuit blocks by state space-guided transient simulation

In this contribution a novel methodology for verification of analog circuit blocks with the aim of full coverage of the analog state space is proposed. On a discretized state space model of the analog system, an efficient state space-guided input stimuli generation algorithm produces piecewise linear input stimuli for every input of the system under verification. Processed by a conventional transient circuit simulator, the simulation results are covering the system's complete dynamic behavior. Simulation by complete state space-covering input stimuli guarantees the verification results to be sound for every possible state and input stimulus of the circuit under verification, which increases the significance of property verification and equivalence checking of transistor netlists versus behavioral models. The application to example circuits shows the feasibility of the approach.