Implementation of a transaction level assertion framework in systemC

Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

45 Zitate (Scopus)

Abstract

Current hardware design and verification methodologies reflect a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Since transaction level models (TLMs) are used for early prototyping and as reference models for the verification of their RTL representation, the quality assurance of TLMs is vital. Assertion based verification (ABV) of RTL models has improved quality assurance of IP blocks and SoC systems to a great extent. Since mapping of an RTL ABV methodology to TL poses severe problems due to different design paradigms, current ABV approaches need extensions towards TL. In this paper we present a prototype implementation of a TL assertion framework using SystemC which is currently the de facto standard for system modeling.

OriginalspracheEnglisch
TitelProceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
Seiten894-899
Seitenumfang6
DOIs
PublikationsstatusVeröffentlicht - 2007
Extern publiziertJa
Veranstaltung2007 Design, Automation and Test in Europe Conference and Exhibition - Nice Acropolis, Frankreich
Dauer: 16 Apr. 200720 Apr. 2007

Publikationsreihe

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Konferenz

Konferenz2007 Design, Automation and Test in Europe Conference and Exhibition
Land/GebietFrankreich
OrtNice Acropolis
Zeitraum16/04/0720/04/07

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