TY - GEN
T1 - Implementation and Evaluation of Adaptive Cache Insertion Policies for Real-Time Systems
AU - Araujo, Bruna Arruda
AU - Gracioli, Giovani
AU - Kloda, Tomasz
AU - Hoornaert, Denis
AU - Caccamo, Marco
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - Memory caches are a key source of unpredictability in today's cyber-physical systems. This fact is mainly due to the high time penalties caused by cache misses. A block that needs to be replaced may need up to 100 times more cycles than a block already in the cache (cache hit). Several studies in the area of realtime systems were carried out aiming to minimize the impact of cache memories on the Worst-Case Execution Time (WCET) of real-time systems. The main approaches are related to cache line replacement policies and cache partitioning mechanisms, as the LRU-based adaptive insertion policies LIP, BIP and DIP, which were developed to try to mitigate the trashing problem of LRU. Several studies have already proven that replacement policies can be influenced by cache parameters, but none of them presented an analysis of the impact of these parameters on policies applied to cache partitions.In this scenario, this work aims to provide an analysis of the impact that cache-related parameters have on the adaptive cache insertion policies applied to a set of benchmarks. For this, we used a cache profile simulator. The results obtained prove that parameters as cache partition size and the number of ways, in fact, play an important factor in the performance and schedulability of applications.
AB - Memory caches are a key source of unpredictability in today's cyber-physical systems. This fact is mainly due to the high time penalties caused by cache misses. A block that needs to be replaced may need up to 100 times more cycles than a block already in the cache (cache hit). Several studies in the area of realtime systems were carried out aiming to minimize the impact of cache memories on the Worst-Case Execution Time (WCET) of real-time systems. The main approaches are related to cache line replacement policies and cache partitioning mechanisms, as the LRU-based adaptive insertion policies LIP, BIP and DIP, which were developed to try to mitigate the trashing problem of LRU. Several studies have already proven that replacement policies can be influenced by cache parameters, but none of them presented an analysis of the impact of these parameters on policies applied to cache partitions.In this scenario, this work aims to provide an analysis of the impact that cache-related parameters have on the adaptive cache insertion policies applied to a set of benchmarks. For this, we used a cache profile simulator. The results obtained prove that parameters as cache partition size and the number of ways, in fact, play an important factor in the performance and schedulability of applications.
KW - Cache replacement policy
KW - Dynamic insertion policy
KW - Real-time systems
UR - http://www.scopus.com/inward/record.url?scp=85123006517&partnerID=8YFLogxK
U2 - 10.1109/SBESC53686.2021.9628309
DO - 10.1109/SBESC53686.2021.9628309
M3 - Conference contribution
AN - SCOPUS:85123006517
T3 - Brazilian Symposium on Computing System Engineering, SBESC
BT - 2021 11th Brazilian Symposium on Computing Systems Engineering, SBESC 2021
PB - IEEE Computer Society
T2 - 11th Brazilian Symposium on Computing Systems Engineering, SBESC 2021
Y2 - 22 November 2021 through 25 November 2021
ER -