IBM PowerNP network processor: Hardware, software, and applications

James R. Allen, Brian M. Bass, Claude Basso, Richard H. Boivie, Jean L. Calvignac, Gordon T. Davis, Laurent Frelechoux, Marco Heddes, Andreas Herkersdorf, Andreas Kind, Joe F. Logan, Mohammad Peyravian, Mark A. Rinaldi, Ravi K. Sabhikhi, Michael S. Siegel, Marcel Waldvogel

Publikation: Beitrag in FachzeitschriftÜbersichtsartikelBegutachtung

67 Zitate (Scopus)


Deep packet processing is migrating to the edges of service provider networks to simplify and speed up core functions. On the other hand, the cores of such networks are migrating to the switching of high-speed traffic aggregates. As a result, more services will have to be performed at the edges, on behalf of both the core and the end users. Associated network equipment will therefore require high flexibility to support evolving high-level services as well as extraordinary performance to deal with the high packet rates. Whereas, in the past, network equipment was based either on general-purpose processors (GPPs) or application-specific integrated circuits (ASICs), favoring flexibility over speed or vice versa, the network processor approach achieves both flexibility and performance. The key advantage of network processors is that hardware-level performance is complemented by flexible software architecture. This paper provides an overview of the IBM PowerNP(tm) NP4GS3 network processor and how it addresses these issues. Its hardware and software design characteristics and its comprehensive base operating software make it well suited for a wide range of networking applications.

Seiten (von - bis)177-193
FachzeitschriftIBM Journal of Research and Development
PublikationsstatusVeröffentlicht - 2003
Extern publiziertJa


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