How to Keep 4-Eyes Principle in a Design and Property Generation Flow

We proposed an approach for automating both RTL and verification code by following the 4EP. The approach uses DSLs to describe RTL and properties in a high-level language and presents a novel design automation flow. The combined usage of meta-model based automation framework and adaptation of MDA vision for code vision has significantly improved the productivity and quality of designs. The approach proposes to translate informal specifications to formal specifications as the starting step. The generation flows for RTL and properties take separate paths from formal specifications to obey 4EP and ensure unknown RTL bugs are not hidden by the generation flow. The presented flow is an ideal alternative to time tedious manual coding of RTL designs with existing HDLs, as the DSLs are custom-tailored to describe the intended hardware without considering the platform specific details.

A significant issue in the semi-conductor industry is ‘design productivity’, which is fast diminishing due to the constant growth in the complexity of system-on-chips and FPGAs. An important counter measure is automating development tasks such as RTL design and properties for functional verification. Frameworks that automate both design and verification tasks must satisfy 4-eyes principle as a basic requirement to ensure the quality of generated designs. In this paper, we present an generation approach developed to obey 4-eyes principle and is used to generate both RTL designs and properties for verification. The approach has been successfully used to generate RISC V processor core and several peripheral devices. The automation approach has resulted in significant reduction in the manual efforts needed and improvements in the quality of generated designs.