Full-Chip Power Density and Thermal Map Characterization for Commercial Microprocessors Under Heat Sink Cooling

Jinwei Zhang, Sheriff Sadiqbatcha, Michael O'Dea, Hussam Amrouch, Sheldon X.D. Tan

Publikation: Beitrag in FachzeitschriftArtikelBegutachtung

12 Zitate (Scopus)

Abstract

In this article, we address the problem of accurate full-chip power and thermal map estimation for commercial off-the-shelf multicore processors. Processors operating with heat sink cooling remains a challenging problem due to the difficulty in direct measurement. We first propose an accurate full-chip steady-state power density map estimation method for commercial multicore microprocessors. The new method consists of a few steps. First, 2-D spatial Laplace operation is performed on the measured thermal maps (images) without heat sink to obtain the so-called raw power maps. Then, a novel scheme is developed to generate the true power density maps from the raw power density maps. The new approach is based on thermal measurements of the processor with back-side cooling using an advanced infrared (IR) thermal imaging system. FEM thermal model constructed in COMSOL Multiphysics is used to validate the estimated power density maps and thermal conductivity. Later, this work creates a high-fidelity FEM thermal model with heat sink and reconstructs the full-chip thermal maps while the heat sink is on. Ensuring that power maps are similar under back cooling and heat sink cooling settings, the reconstructed thermal maps are verified by the matching between the on-chip thermal sensor readings and the corresponding elements of thermal maps. Experiments on an Intel i7-8650U 4-core processor with back cooling shows 96% similarity (2-D correlation) between the measured thermal maps and the thermal maps reconstructed from the estimated power maps, with 1.3 °C average absolute error. Under heat sink cooling, the average absolute error is 2.2 °C over a 56 °C temperature range and about 3.9% error between the computed and the real thermal maps at the sensor locations. Furthermore, the proposed power map estimation method achieves higher resolution and at least 100× speedup than a recently proposed state-of-art Blind Power Identification method.

OriginalspracheEnglisch
Seiten (von - bis)1453-1466
Seitenumfang14
FachzeitschriftIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Jahrgang41
Ausgabenummer5
DOIs
PublikationsstatusVeröffentlicht - 1 Mai 2022
Extern publiziertJa

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