Formal approaches to analog circuit verification

Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Wang Yifan

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

17 Zitate (Scopus)

Abstract

For a speed-up of analog design cycles to keep up with the continuously decreasing time to market, iterative design refinement and redesigns are more than ever regarded as showstoppers. To deal with this issue, referred to as design and verification gap, the development of a continuous and consistent verification is mandatory. In digital design, formal verification methods are considered as a key technology for efficient design flows. However, industrial availability of formal methods for analog circuit verification is still negligible despite a growing need. In recent years, research institutions have made considerable advances in the area of formal verification of analog circuits. This paper presents a selection of four recent approaches in analog verification that cover a broad scope of verification philosophies.

OriginalspracheEnglisch
TitelProceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers Inc.
Seiten724-729
Seitenumfang6
ISBN (Print)9783981080155
DOIs
PublikationsstatusVeröffentlicht - 2009
Extern publiziertJa
Veranstaltung2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 - Nice, Frankreich
Dauer: 20 Apr. 200924 Apr. 2009

Publikationsreihe

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Konferenz

Konferenz2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
Land/GebietFrankreich
OrtNice
Zeitraum20/04/0924/04/09

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