TY - GEN
T1 - Ferroelectric FET Threshold Voltage Optimization for Reliable In-Memory Computing
AU - Prakash, Om
AU - Ni, Kai
AU - Amrouch, Hussam
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Ferroelectric FET (FeFET) emerges as a highly promising candidate for in-memory computing due to its outstanding performance, superior energy efficiency and great scalability. For FeFET, generally the memory window, i.e., the separation between the two threshold voltage (VTH) states, is of interest. The absolute value of the low-VTH and high-VTH states are generally not scrutinized. However, in this work, we demonstrate that a proper engineering of VTH is necessary to ensure correct array operation for in-memory computing applications. We highlight that for all the current-based operations, it is necessary to keep both the VTH states positive to cut off the leakage for grounded unselected cells. To reach that design target, we systematically evaluate various design options for VTH engineering, including the gate metal work function, the body bias, and the buried oxide thickness, in a fully-depleted silicon-on-insulator (FDSOI) FeFET using calibrated TCAD simulations. We establish the design guidelines for VTH engineering to ensure successful operation of in-memory computing applications.
AB - Ferroelectric FET (FeFET) emerges as a highly promising candidate for in-memory computing due to its outstanding performance, superior energy efficiency and great scalability. For FeFET, generally the memory window, i.e., the separation between the two threshold voltage (VTH) states, is of interest. The absolute value of the low-VTH and high-VTH states are generally not scrutinized. However, in this work, we demonstrate that a proper engineering of VTH is necessary to ensure correct array operation for in-memory computing applications. We highlight that for all the current-based operations, it is necessary to keep both the VTH states positive to cut off the leakage for grounded unselected cells. To reach that design target, we systematically evaluate various design options for VTH engineering, including the gate metal work function, the body bias, and the buried oxide thickness, in a fully-depleted silicon-on-insulator (FDSOI) FeFET using calibrated TCAD simulations. We establish the design guidelines for VTH engineering to ensure successful operation of in-memory computing applications.
KW - FDSOI
KW - FeFET
KW - In-Memory Computing
KW - TCAM
UR - http://www.scopus.com/inward/record.url?scp=85130763170&partnerID=8YFLogxK
U2 - 10.1109/IRPS48227.2022.9764551
DO - 10.1109/IRPS48227.2022.9764551
M3 - Conference contribution
AN - SCOPUS:85130763170
T3 - IEEE International Reliability Physics Symposium Proceedings
SP - 9C31-9C310
BT - 2022 IEEE International Reliability Physics Symposium, IRPS 2022 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE International Reliability Physics Symposium, IRPS 2022
Y2 - 27 March 2022 through 31 March 2022
ER -