TY - GEN
T1 - Fault-effect analysis on system-level hardware modeling using virtual prototypes
AU - Tabacaru, Bogdan Andrei
AU - Chaari, Moomen
AU - Ecker, Wolfgang
AU - Kruse, Thomas
AU - Novello, Cristiano
N1 - Publisher Copyright:
© 2016 ECSI.
PY - 2016/7/2
Y1 - 2016/7/2
N2 - Safety-critical systems-on-chip currently undergo extensive fault-effect analyses. To meet the safety requirements of ISO 26262, most frequently fault-injection campaigns are per-formed. Due to the exponentially growing fault-verification space, faster simulation possibilities than enabled by register transfer (RT) and gate-level (GL) models are under investigation. Fault injection on virtual prototypes (VPs) is one measure to speed up simulation. However, VPs require the injection of complex abstract faults to observe the same effects of, for example, single-bit fault injection into GL models. As a consequence, VPs often suffer from injection of incorrect faults (i.e., faults whose effects cannot be reproduced on the RT or gate levels). Therefore, we developed an efficient approach to verify or falsify failures detected with VP fault simulation. As a result, incorrect faults are discovered early in the development phase helping to improve the design of accurate safety mechanisms. Moreover, the exclusion of incorrect faults from fault-effect analyses further improves the accuracy and efficiency of fault-injection campaigns. The benefit of the presented method has been validated using a medium-size controller design.
AB - Safety-critical systems-on-chip currently undergo extensive fault-effect analyses. To meet the safety requirements of ISO 26262, most frequently fault-injection campaigns are per-formed. Due to the exponentially growing fault-verification space, faster simulation possibilities than enabled by register transfer (RT) and gate-level (GL) models are under investigation. Fault injection on virtual prototypes (VPs) is one measure to speed up simulation. However, VPs require the injection of complex abstract faults to observe the same effects of, for example, single-bit fault injection into GL models. As a consequence, VPs often suffer from injection of incorrect faults (i.e., faults whose effects cannot be reproduced on the RT or gate levels). Therefore, we developed an efficient approach to verify or falsify failures detected with VP fault simulation. As a result, incorrect faults are discovered early in the development phase helping to improve the design of accurate safety mechanisms. Moreover, the exclusion of incorrect faults from fault-effect analyses further improves the accuracy and efficiency of fault-injection campaigns. The benefit of the presented method has been validated using a medium-size controller design.
KW - Automotive
KW - Fault Injection
KW - ISO 26262
KW - Safety Verification
KW - SystemC
KW - TLM
KW - Verilator
KW - Virtual Prototyping
UR - http://www.scopus.com/inward/record.url?scp=85017117471&partnerID=8YFLogxK
U2 - 10.1109/FDL.2016.7880368
DO - 10.1109/FDL.2016.7880368
M3 - Conference contribution
AN - SCOPUS:85017117471
T3 - Forum on Specification and Design Languages
BT - FDL 2016 - 2016 Forum on Specification and Design Languages, Proceedings
PB - IEEE Computer Society
T2 - 2016 Forum on Specification and Design Languages, FDL 2016
Y2 - 14 September 2016 through 16 September 2016
ER -