Fast evaluation of analog circuit structures by polytopal approximations

D. Mueller, G. Stehr, H. Graeb, U. Schlichtmann

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

3 Zitate (Scopus)

Abstract

In this paper we present a method for the fast evaluation of circuit structures. It is part of a methodology for the structural synthesis of analog circuits which generates a large number of different circuit structures. Goal of the presented methods is to And circuit structures, which fit best the design goals. Based on implicit analog circuit specifications, as well as explicit performance specifications given by the designer, the presented method approximates the feasible region of parameters by a polytope. This polytopal approximation of the performance capabilities can be calculated and visualized or the feasibility of the specification can be tested by linear programming. The method has been validated on a set of Operational Amplifier structures.

OriginalspracheEnglisch
TitelISCAS 2006
Untertitel2006 IEEE International Symposium on Circuits and Systems, Proceedings
Seiten1479-1482
Seitenumfang4
PublikationsstatusVeröffentlicht - 2006
VeranstaltungISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Griechenland
Dauer: 21 Mai 200624 Mai 2006

Publikationsreihe

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Konferenz

KonferenzISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Land/GebietGriechenland
OrtKos
Zeitraum21/05/0624/05/06

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