Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level Designs

Keyphrases

• Analysis Cycle 12%
• Architecture Search 25%
• Block-based 25%
• Boundary Optimization 12%
• Coefficient of Determination 12%
• Cross-boundary 12%
• Design Flow 12%
• Intermediate Representation 12%
• Level Design 100%
• Machine Learning 25%
• Microarchitecture 37%
• Netlist 25%
• Recent Approaches 12%
• Register Transfer Level 100%
• Required Time of Arrival 12%
• Synthesis Tool 12%
• Time Estimation 100%
• Time Metrics 37%
• Time of Arrival 62%
• Timer 100%
• Timing Violation 12%
• Timing-driven 12%

Computer Science

• Cycle Analysis 12%
• Intermediate Representation 12%
• Learning System 25%
• Level Synthesis 12%
• Machine Learning 25%
• Microarchitecture 37%
• Register-Transfer Level 100%
• Synthesis Tool 12%