TY - GEN
T1 - Error Correction for Partially Stuck Memory Cells
AU - Al Kim, Haider
AU - Puchinger, Sven
AU - Wachter-Zeh, Antonia
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - We present code constructions for masking u partially stuck memory cells with q levels and correcting additional random errors. The results are achieved by combining the methods for masking and error correction for stuck cells in [1] with the masking-only results for partially stuck cells in [2]. We present two constructions for masking u < q cells and error correction: one is general and based on a generator matrix of a specific form. The second construction uses cyclic codes and allows to efficiently bound the error-correction capability using the BCH bound. Furthermore, we extend the results to masking u ≥ q cells. For u > 1 and q > 2, all new constructions require less redundancy for masking partially stuck cells than previous work on stuck cells, which in turn can result in higher code rates at the same masking and error correction capability.
AB - We present code constructions for masking u partially stuck memory cells with q levels and correcting additional random errors. The results are achieved by combining the methods for masking and error correction for stuck cells in [1] with the masking-only results for partially stuck cells in [2]. We present two constructions for masking u < q cells and error correction: one is general and based on a generator matrix of a specific form. The second construction uses cyclic codes and allows to efficiently bound the error-correction capability using the BCH bound. Furthermore, we extend the results to masking u ≥ q cells. For u > 1 and q > 2, all new constructions require less redundancy for masking partially stuck cells than previous work on stuck cells, which in turn can result in higher code rates at the same masking and error correction capability.
KW - (partially) stuck cells
KW - BCH code
KW - defective cells
KW - error correction
KW - flash memories
KW - partitioned cyclic codes
KW - phase change memories
UR - http://www.scopus.com/inward/record.url?scp=85081618280&partnerID=8YFLogxK
U2 - 10.1109/REDUNDANCY48165.2019.9003352
DO - 10.1109/REDUNDANCY48165.2019.9003352
M3 - Conference contribution
AN - SCOPUS:85081618280
T3 - 2019 16th International Symposium "Problems of Redundancy in Information and Control Systems", REDUNDANCY 2019
SP - 87
EP - 92
BT - 2019 16th International Symposium "Problems of Redundancy in Information and Control Systems", REDUNDANCY 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th International Symposium "Problems of Redundancy in Information and Control Systems", REDUNDANCY 2019
Y2 - 21 October 2019 through 25 October 2019
ER -