Effective Processor Model Generation from Instruction Set Simulator to Hardware Design

As the complexity of modern processing systems continues to increase, there has been a growing interest in the application of reusable code generators for hardware design. However, a formal system specification must be provided for such generators to be effective. Code generation has become a promising solution in the processor domain, where the Instruction Set Architecture (ISA) provides a natural system-level abstraction. In this paper, we present a holistic generator framework that produces variable microarchitecture designs, as well as relevant models for validation and formal verification. Our approach involves generating multiple functionally consistent models across different levels of abstraction using a unified formal ISA specification. By adhering to the 4-eyes principle of verification, we demonstrate that our framework minimizes the risk of common-mode errors that would typically escape the design verification process. Additionally, our code generators significantly reduce the manual development effort and generate high-performing instruction set simulators.