Early RTL delay prediction using neural networks

Keyphrases

• Analysis-by-synthesis 20%
• Best Model 20%
• Chip Design 20%
• Coefficient of Determination 20%
• Combinational Circuits 20%
• Computationally Expensive 20%
• Delay Estimation 40%
• Delay Prediction 100%
• Design Flow 60%
• Design Iteration 20%
• Different Datasets 20%
• Digital chip 20%
• Early Design Phases 20%
• Formal Specification 20%
• Ground-truth Labels 20%
• Hardware Generators 20%
• Interdependency 20%
• Level Design 20%
• Level Model 20%
• Logic Gates 20%
• Logic Synthesis 20%
• Machine Learning-based Approach 20%
• Microarchitecture 40%
• Model Performance 20%
• Multiplexer 20%
• Neural Network 100%
• Open-source Tools 20%
• Prefix Adders 20%
• Register Transfer Level 100%
• Resolving Time 20%
• S-lay 20%
• Static Timing Analysis 20%
• Timing Analysis 20%
• Training Data 20%

Computer Science

• Bit Prefix Adder 20%
• Combinational Circuit 20%
• Computer Hardware 20%
• Design Iteration 20%
• Early Design Stage 20%
• Formal Specification 20%
• Hardware Designer 20%
• Interdependency 20%
• Logic Gate 20%
• Logic Synthesis 20%
• Machine Learning-Based Approach 20%
• Microarchitecture 40%
• Multiplexer 20%
• Neural Network 100%
• Open Source Tool 20%
• Performance Model 20%
• Register-Transfer Level 100%
• Timing Analysis 40%
• Training Data 20%

Engineering

• Adders 33%
• And Logic Gate 33%
• Classical Method 33%
• Combinatorial Circuits 33%
• Delay Estimation 66%
• Design Flow 100%
• Design Iteration 33%
• Design Stage 33%
• Interdependency 33%
• Learning System 33%
• Level Model 33%
• Logic Synthesis 33%
• Multiplexer 33%