Dual supply voltage scaling in a conventional power-driven logic synthesis environment

Torsten Mahnke; Walter Stechele; Wolfgang Hoeld

doi:10.1007/3-540-45716-x_15

Dual supply voltage scaling in a conventional power-driven logic synthesis environment

Torsten Mahnke, Walter Stechele, Wolfgang Hoeld

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Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

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Abstract

Dual supply voltage scaling (DSVS) is an emerging technique in logic-level power optimization. In this paper, a novel design methodology, which enables DSVS to be carried out in a state-of-the-art environment for power-driven logic synthesis, is presented. The idea is to provide a dual supply voltage standard cell library modeled such that a typical gate sizing algorithm can be exploited for DSVS. Since this approach renders dedicated DSVS algorithms superfluous, only little modification of established design flows is required. The methodology has been applied to MCNC benchmark circuits. Compared to the results of single supply voltage power-driven logic synthesis, additional power reductions of 10% on average and 24% in the best case have been achieved.

Originalsprache	Englisch
Titel	Integrated Circuit Design
Untertitel	Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings
Redakteure/-innen	Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido
Herausgeber (Verlag)	Springer Verlag
Seiten	146-155
Seitenumfang	10
ISBN (Print)	9783540441434
DOIs	https://doi.org/10.1007/3-540-45716-x_15
Publikationsstatus	Veröffentlicht - 2002
Veranstaltung	12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002 - Seville, Spanien Dauer: 11 Sept. 2002 → 13 Sept. 2002

Publikationsreihe

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Band	2451
ISSN (Print)	0302-9743
ISSN (elektronisch)	1611-3349

Konferenz

Konferenz	12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002
Land/Gebiet	Spanien
Ort	Seville
Zeitraum	11/09/02 → 13/09/02

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10.1007/3-540-45716-x_15

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Mahnke, T., Stechele, W., & Hoeld, W. (2002). Dual supply voltage scaling in a conventional power-driven logic synthesis environment. in B. Hochet, A. J. Acosta, & M. J. Bellido (Hrsg.), Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings (S. 146-155). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Band 2451). Springer Verlag. https://doi.org/10.1007/3-540-45716-x_15

Mahnke, Torsten ; Stechele, Walter ; Hoeld, Wolfgang. / Dual supply voltage scaling in a conventional power-driven logic synthesis environment. Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings. Hrsg. / Bertrand Hochet ; Antonio J. Acosta ; Manuel J. Bellido. Springer Verlag, 2002. S. 146-155 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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abstract = "Dual supply voltage scaling (DSVS) is an emerging technique in logic-level power optimization. In this paper, a novel design methodology, which enables DSVS to be carried out in a state-of-the-art environment for power-driven logic synthesis, is presented. The idea is to provide a dual supply voltage standard cell library modeled such that a typical gate sizing algorithm can be exploited for DSVS. Since this approach renders dedicated DSVS algorithms superfluous, only little modification of established design flows is required. The methodology has been applied to MCNC benchmark circuits. Compared to the results of single supply voltage power-driven logic synthesis, additional power reductions of 10% on average and 24% in the best case have been achieved.",

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Mahnke, T, Stechele, W & Hoeld, W 2002, Dual supply voltage scaling in a conventional power-driven logic synthesis environment. in B Hochet, AJ Acosta & MJ Bellido (Hrsg.), Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Bd. 2451, Springer Verlag, S. 146-155, 12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002, Seville, Spanien, 11/09/02. https://doi.org/10.1007/3-540-45716-x_15

Dual supply voltage scaling in a conventional power-driven logic synthesis environment. / Mahnke, Torsten; Stechele, Walter; Hoeld, Wolfgang.
Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings. Hrsg. / Bertrand Hochet; Antonio J. Acosta; Manuel J. Bellido. Springer Verlag, 2002. S. 146-155 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Band 2451).

Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

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N2 - Dual supply voltage scaling (DSVS) is an emerging technique in logic-level power optimization. In this paper, a novel design methodology, which enables DSVS to be carried out in a state-of-the-art environment for power-driven logic synthesis, is presented. The idea is to provide a dual supply voltage standard cell library modeled such that a typical gate sizing algorithm can be exploited for DSVS. Since this approach renders dedicated DSVS algorithms superfluous, only little modification of established design flows is required. The methodology has been applied to MCNC benchmark circuits. Compared to the results of single supply voltage power-driven logic synthesis, additional power reductions of 10% on average and 24% in the best case have been achieved.

AB - Dual supply voltage scaling (DSVS) is an emerging technique in logic-level power optimization. In this paper, a novel design methodology, which enables DSVS to be carried out in a state-of-the-art environment for power-driven logic synthesis, is presented. The idea is to provide a dual supply voltage standard cell library modeled such that a typical gate sizing algorithm can be exploited for DSVS. Since this approach renders dedicated DSVS algorithms superfluous, only little modification of established design flows is required. The methodology has been applied to MCNC benchmark circuits. Compared to the results of single supply voltage power-driven logic synthesis, additional power reductions of 10% on average and 24% in the best case have been achieved.

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Mahnke T, Stechele W, Hoeld W. Dual supply voltage scaling in a conventional power-driven logic synthesis environment. in Hochet B, Acosta AJ, Bellido MJ, Hrsg., Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings. Springer Verlag. 2002. S. 146-155. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/3-540-45716-x_15

Dual supply voltage scaling in a conventional power-driven logic synthesis environment

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