TY - GEN
T1 - Diagnosis-aware system design for automotive E/E architectures
AU - Waszecki, Peter
AU - Sagstetter, Florian
AU - Lukasiewycz, Martin
AU - Chakraborty, Samarjit
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2015/2/2
Y1 - 2015/2/2
N2 - This paper proposes a schedule synthesis approach taking fault diagnosis and testability into account at design time. Over the last years, the amount of automotive software and hardware has been successively growing. As a consequence, the complexity of present-day Electrical and Electronic (E/E) architectures reached a state where current fault detection mechanisms are often not sufficient or computationally too expensive to guarantee a reliable system functionality. As a remedy, we propose a novel design methodology, optimizing a subsequent fault diagnosis in terms of the necessary detection time as well as the diagnostic resolution. Our approach is based on a time-triggered architecture and aims at a decentralized message-based fault diagnosis solution. In order to increase the system reliability, during schedule synthesis a modified and adapted message distribution is taken into account which additionally considers previously undiagnosable resources. While our approach might lead to a slightly increased bandwidth utilization, it clearly improves the overall diagnosis of faulty resources by a reduced detection time and an increased diagnostic resolution.
AB - This paper proposes a schedule synthesis approach taking fault diagnosis and testability into account at design time. Over the last years, the amount of automotive software and hardware has been successively growing. As a consequence, the complexity of present-day Electrical and Electronic (E/E) architectures reached a state where current fault detection mechanisms are often not sufficient or computationally too expensive to guarantee a reliable system functionality. As a remedy, we propose a novel design methodology, optimizing a subsequent fault diagnosis in terms of the necessary detection time as well as the diagnostic resolution. Our approach is based on a time-triggered architecture and aims at a decentralized message-based fault diagnosis solution. In order to increase the system reliability, during schedule synthesis a modified and adapted message distribution is taken into account which additionally considers previously undiagnosable resources. While our approach might lead to a slightly increased bandwidth utilization, it clearly improves the overall diagnosis of faulty resources by a reduced detection time and an increased diagnostic resolution.
UR - http://www.scopus.com/inward/record.url?scp=84924308398&partnerID=8YFLogxK
U2 - 10.1109/ISICIR.2014.7029550
DO - 10.1109/ISICIR.2014.7029550
M3 - Conference contribution
AN - SCOPUS:84924308398
T3 - Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014
SP - 456
EP - 459
BT - Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th International Symposium on Integrated Circuits, ISIC 2014
Y2 - 10 December 2014 through 12 December 2014
ER -