Design of a Low Multi-Loop Inductance Three Level Neutral Point Clamped Inverter with GaN HEMTs

This work shows a numerical and experimental analysis of a Neutral-Point-Clamp (NPC) three level inverter featuring an ultra low inductance printed circuit board (PCB) design in consideration of the mutual inductive and capacitive couplings. The commutation loops in this design are found to be strongly dependent on the vertical thickness of the used prepregs and the core. For vertical thicknesses = 100 µm capacitive coupling must be taken into account in the switching cell design. Experimental measurements of a test set-up with a total PCB thickness of 400 µm results in commutation loop inductances from 1.4 nH up to 3.1 nH. In this set-up, switching tests without external gate resistor showed only a maximum voltage overshoot of 7% at 800 V. Based on a numerical analysis of the NPC cell we propose a further switching performance improvement with significant smaller parasitic inductance due to the application of novel printed circuit technologies such as the integration of bare dies into the printed circuit board or polyimide as an interlayer dielectric material.