Design Cube - a model for VHDL designflow representation

Hardware design under the use of the hardware description language VHDL has to consider three independent property scales that influence the design process from an abstract level to gate level, namely the design view, the timing aspect, and the value representation. The well known Y-chart model is not suitable to describe these property scales in a satisfactory way; furthermore, this model contains the aspects of placement and routing, which are not supported by VHDL due to the fact that these steps are performed by conventional tools. In this paper, a new model for the design flow representation with the particular view on VHDL is presented.