TY - GEN
T1 - Design centric modeling of digital hardware
AU - Schreiner, Johannes
AU - Findenigy, Rainer
AU - Ecker, Wolfgang
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/11/17
Y1 - 2016/11/17
N2 - Today's dominant RTL languages, VHDL and (System) Verilog, were designed as description and simulation languages. Therefore, they have a clearly defined - but not in all cases deterministic - simulation algorithm as backbone of the language definition. Both languages have been adopted as RTL design languages but still impose a lot of simulation/synthesis mismatches. As a further disadvantage, considerable overhead can be needed to code well-known hardware patterns such as FSMs. Finally, the simulation algorithm prevents efficient simulation (e.g. two-state or cycle-based simulation) as well as advanced model analysis (e.g. X-propagation) or fosters an execution that is not in sync with the language definition. Therefore, we developed a design centric modeling approach that allows a clear specification of the design intent and provides freedom for various target HDLs and modeling styles. Since our approach is specified without underlying simulation semantics, we provide a formal definition considering only certain points in simulation traces, thus enabling various ways for simulation. To avoid syntactic sugar, we selected a metamodeling based approach, which we use as part of a modeldriven generation-focused design approach.
AB - Today's dominant RTL languages, VHDL and (System) Verilog, were designed as description and simulation languages. Therefore, they have a clearly defined - but not in all cases deterministic - simulation algorithm as backbone of the language definition. Both languages have been adopted as RTL design languages but still impose a lot of simulation/synthesis mismatches. As a further disadvantage, considerable overhead can be needed to code well-known hardware patterns such as FSMs. Finally, the simulation algorithm prevents efficient simulation (e.g. two-state or cycle-based simulation) as well as advanced model analysis (e.g. X-propagation) or fosters an execution that is not in sync with the language definition. Therefore, we developed a design centric modeling approach that allows a clear specification of the design intent and provides freedom for various target HDLs and modeling styles. Since our approach is specified without underlying simulation semantics, we provide a formal definition considering only certain points in simulation traces, thus enabling various ways for simulation. To avoid syntactic sugar, we selected a metamodeling based approach, which we use as part of a modeldriven generation-focused design approach.
KW - Design Productivity
KW - Hardware Generation
KW - Model Driven Architecture
KW - Model-of-Design (MoD)
KW - Model-of-Things (MoT)
UR - http://www.scopus.com/inward/record.url?scp=85006409639&partnerID=8YFLogxK
U2 - 10.1109/HLDVT.2016.7748254
DO - 10.1109/HLDVT.2016.7748254
M3 - Conference contribution
AN - SCOPUS:85006409639
T3 - 2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016
SP - 46
EP - 52
BT - 2016 IEEE International High Level Design Validation and Test Workshop, HLDVT 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 18th IEEE International High Level Design Validation and Test Workshop, HLDVT 2016
Y2 - 7 October 2016 through 8 October 2016
ER -