Considering nearest neighbor constraints of quantum circuits at the reversible circuit level

Since many underlying quantum algorithms include a Boolean component, synthesis of the respective circuits is often conducted by a two-stage procedure: First, a reversible circuit realizing the Boolean component is generated. Afterwards, this circuit is mapped into a respective quantum gate cascade. In addition, recent physical accomplishments have led to further issues to be considered, e.g. nearest neighbor constraints. However, due to the lack of proper metrics, these constraints usually have been addressed at the quantum circuit level only. In this paper, we present an approach that allows the consideration of nearest neighbor constraints already at the reversible circuit level. For this purpose, a recently introduced gate library is assumed for which a proper metric is proposed. By means of an optimization approach, the applicability of the proposed scheme is illustrated.