Abstract
The Universal Verification Methodology (UVM) has become a de facto standard in today's functional verification of digital designs. However, it is rarely used for the verification of Designs Under Test containing Real Number Models. This paper presents a new technique using UVM that can be used in order to compare models of analog circuitry on different levels of abstraction. It makes use of statistic metrics. The presented technique enables us to ensure that Real Number Models used in chip projects match the transistor level circuitry during the whole life cycle of the project.
Originalsprache | Englisch |
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Titel | 2013 International Symposium on System-on-Chip, SoC 2013 - Proceedings |
Herausgeber (Verlag) | IEEE Computer Society |
ISBN (Print) | 9781479911899 |
DOIs | |
Publikationsstatus | Veröffentlicht - 2013 |
Extern publiziert | Ja |
Veranstaltung | 2013 15th International Symposium on System-on-Chip, SoC 2013 - Tampere, Finnland Dauer: 23 Okt. 2013 → 24 Okt. 2013 |
Publikationsreihe
Name | 2013 International Symposium on System-on-Chip, SoC 2013 - Proceedings |
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Konferenz
Konferenz | 2013 15th International Symposium on System-on-Chip, SoC 2013 |
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Land/Gebiet | Finnland |
Ort | Tampere |
Zeitraum | 23/10/13 → 24/10/13 |