Comparison of analog transactions using statistics

Alexander W. Rath, Volkan Esen, Wolfgang Ecker

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

1 Zitat (Scopus)

Abstract

The Universal Verification Methodology (UVM) has become a de facto standard in today's functional verification of digital designs. However, it is rarely used for the verification of Designs Under Test containing Real Number Models. This paper presents a new technique using UVM that can be used in order to compare models of analog circuitry on different levels of abstraction. It makes use of statistic metrics. The presented technique enables us to ensure that Real Number Models used in chip projects match the transistor level circuitry during the whole life cycle of the project.

OriginalspracheEnglisch
Titel2013 International Symposium on System-on-Chip, SoC 2013 - Proceedings
Herausgeber (Verlag)IEEE Computer Society
ISBN (Print)9781479911899
DOIs
PublikationsstatusVeröffentlicht - 2013
Extern publiziertJa
Veranstaltung2013 15th International Symposium on System-on-Chip, SoC 2013 - Tampere, Finnland
Dauer: 23 Okt. 201324 Okt. 2013

Publikationsreihe

Name2013 International Symposium on System-on-Chip, SoC 2013 - Proceedings

Konferenz

Konferenz2013 15th International Symposium on System-on-Chip, SoC 2013
Land/GebietFinnland
OrtTampere
Zeitraum23/10/1324/10/13

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