Chip hardware-in-the-loop simulation coupling optimization through new algorithm analysis technique

Hardware-in-the-Loop (HIL) simulation is an important method in the design and validation process of complex hardware/software systems like electronic control units (ECU) for automotive applications. In [1] we presented an approach called Chip Hardware-In-The-Loop Simulation (CHILS) to embed a microcontroller (MC) into different simulation environments. To optimize the coupling between simulation and the MC the different parts of the system have to be analyzed. A numerical analysis of the algorithms used by the programs, which are executed on the MC, can help to find optimized settings for the data exchange between simulation and MC. Numerical error analysis is very costly so our approach combines a precalculated analysis result database with graph matching and recombination of program graphs. The result of the analysis delivers the condition number of the algorithm, so it can be concluded how large will be the influence of an error introduced by the coupling system.