Built-in self test architectures for multistage interconnection networks

E. Bernard; S. Simon; J. A. Nossek

Built-in self test architectures for multistage interconnection networks

E. Bernard, S. Simon, J. A. Nossek

Siemens AG

Publikation: Beitrag in Fachzeitschrift › Konferenzartikel › Begutachtung

1 Zitat (Scopus)

Abstract

A novel built-in self test architecture for locally controlled cube-type N×N multistage interconnection networks (MINs) is presented. First, a state-based pseudoexhaustive test procedure for this class of MINs is outlined. Then, a labelling algorithm on a binary n-cube is described which generates the necessary inputs for the tests. From the dependence graph of this algorithm a tree architecture is derived which results in a hardware overhead of O(1/log N).

Originalsprache	Englisch
Seiten (von - bis)	176-180
Seitenumfang	5
Fachzeitschrift	Proceedings of European Design and Test Conference
Publikationsstatus	Veröffentlicht - 1996
Extern publiziert	Ja
Veranstaltung	Proceedings of the 1996 European Design & Test Conference - Paris, Fr Dauer: 11 März 1996 → 14 März 1996

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@article{64da008aede64c9aa06a326b70b42b46,

title = "Built-in self test architectures for multistage interconnection networks",

abstract = "A novel built-in self test architecture for locally controlled cube-type N×N multistage interconnection networks (MINs) is presented. First, a state-based pseudoexhaustive test procedure for this class of MINs is outlined. Then, a labelling algorithm on a binary n-cube is described which generates the necessary inputs for the tests. From the dependence graph of this algorithm a tree architecture is derived which results in a hardware overhead of O(1/log N).",

author = "E. Bernard and S. Simon and Nossek, {J. A.}",

year = "1996",

language = "English",

pages = "176--180",

journal = "Proceedings of European Design and Test Conference",

issn = "1066-1409",

note = "Proceedings of the 1996 European Design & Test Conference ; Conference date: 11-03-1996 Through 14-03-1996",

}

TY - JOUR

T1 - Built-in self test architectures for multistage interconnection networks

AU - Bernard, E.

AU - Simon, S.

AU - Nossek, J. A.

PY - 1996

Y1 - 1996

N2 - A novel built-in self test architecture for locally controlled cube-type N×N multistage interconnection networks (MINs) is presented. First, a state-based pseudoexhaustive test procedure for this class of MINs is outlined. Then, a labelling algorithm on a binary n-cube is described which generates the necessary inputs for the tests. From the dependence graph of this algorithm a tree architecture is derived which results in a hardware overhead of O(1/log N).

AB - A novel built-in self test architecture for locally controlled cube-type N×N multistage interconnection networks (MINs) is presented. First, a state-based pseudoexhaustive test procedure for this class of MINs is outlined. Then, a labelling algorithm on a binary n-cube is described which generates the necessary inputs for the tests. From the dependence graph of this algorithm a tree architecture is derived which results in a hardware overhead of O(1/log N).

UR - http://www.scopus.com/inward/record.url?scp=0029734629&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0029734629

SN - 1066-1409

SP - 176

EP - 180

JO - Proceedings of European Design and Test Conference

JF - Proceedings of European Design and Test Conference

T2 - Proceedings of the 1996 European Design & Test Conference

Y2 - 11 March 1996 through 14 March 1996

ER -

Built-in self test architectures for multistage interconnection networks

Abstract

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