Beyond DVFS: A first look at performance under a hardware-enforced power bound

Barry Rountree, Dong H. Ahn, Bronis R. De Supinski, David K. Lowenthal, Martin Schulz

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

133 Zitate (Scopus)

Abstract

Dynamic Voltage Frequency Scaling (DVFS) has been the tool of choice for balancing power and performance in high-performance computing (HPC). With the introduction of Intel's Sandy Bridge family of processors, researchers now have a far more attractive option: user-specified, dynamic, hardware-enforced processor power bounds. In this paper we provide a first look at this technology in the HPC environment and detail both the opportunities and potential pitfalls of using this technique to control processor power. As part of this evaluation we measure power and performance for single-processor instances of several of the NAS Parallel Benchmarks. Additionally, we focus on the behavior of a single benchmark, MG, under several different power bounds. We quantify the well-known manufacturing variation in processor power efficiency and show that, in the absence of a power bound, this variation has no correlation to performance. We then show that execution under a power bound translates this variation in efficiency into variation in performance.

OriginalspracheEnglisch
TitelProceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
Seiten947-953
Seitenumfang7
DOIs
PublikationsstatusVeröffentlicht - 2012
Extern publiziertJa
Veranstaltung2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012 - Shanghai, China
Dauer: 21 Mai 201225 Mai 2012

Publikationsreihe

NameProceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012

Konferenz

Konferenz2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012
Land/GebietChina
OrtShanghai
Zeitraum21/05/1225/05/12

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