Automated SoC Hardening with Model Transformation

Fault tolerance enables the system to avoid threats (fail-safe) or continue with its safe operational functionality even in the presence of random faults. This ability comes at the cost of additional development efforts and the silicon overhead required to harden the critical elements. The hardening process adds the safety mechanisms around the critical elements of the system such as registers and memory. In this paper, we present an approach to develop fault-Tolerant systems by automating the hardening process, hence increasing design productivity. The process also helps to reduce overhead by very focused and critically guided insertion of safety mechanisms. By comparing our approach to a commercial generic safety IP, reduced development efforts, simpler integration and less overhead are observed. To demonstrate the applicability, an arbitrary number of registers in an SoC were hardened automatically. The experimental results show that our approach scales with a growing number of safety requirements.