Automated construction of a cycle-approximate transaction level model of a memory controller

Keyphrases

• Automated Construction 100%
• Memory Controller 100%
• Transaction Level Model 100%
• Register Transfer Level 80%
• Timing Behavior 40%
• Challenging Tasks 20%
• Highly Accurate 20%
• Offset Error 20%
• Early Design Phases 20%
• Performance Estimation 20%
• Black Box 20%
• Design Evaluation 20%
• Virtual Prototyping 20%
• Timing Offset 20%
• Level Model 20%
• Conditional Probability Distribution 20%
• System-on-chip Design 20%
• Transaction-level 20%
• RaPID System 20%
• Software Design 20%
• Level Description 20%
• System-on-chip 20%
• Software Development 20%
• Design Exploration 20%
• Chip Simulation 20%

Computer Science

• Level Transaction 100%
• Memory Controller 100%
• Register-Transfer Level 66%
• Timing Behavior 33%
• System-on-Chip 33%
• Estimation Performance 16%
• Design Exploration 16%
• timing offset 16%
• Software Development 16%
• Level Description 16%
• Virtual Prototyping 16%
• Conditional Probability 16%