Application of machine learning methods in post-silicon yield improvement

Baris Yigit, Grace Li Zhang, Bing Li, Yiyu Shi, Ulf Schlichtmann

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

3 Zitate (Scopus)

Abstract

In nanometer scale manufacturing, process variations have a significant impact on circuit performance. To handle them, post-silicon clock tuning buffers can be included into the circuit to balance timing budgets of neighboring critical paths. The state of the art is a sampling-based approach, in which an integer linear programming (ILP) problem must be solved for every sample. The runtime complexity of this approach is the number of samples multiplied by the required time for an ILP solution. Existing work tries to reduce the number of samples but still leaves the problem of a long runtime unsolved. In this paper, we propose a machine learning approach to reduce the runtime by learning the positions and sizes of post-silicon tuning buffers. Experimental results demonstrate that we can predict buffer locations and sizes with a very good accuracy (90% and higher) and achieve a significant yield improvement (up to 18.8%) with a significant speed-up (up to almost 20 times) compared to existing work.

OriginalspracheEnglisch
TitelProceedings - 30th IEEE International System on Chip Conference, SOCC 2017
Redakteure/-innenJurgen Becker, Ramalingam Sridhar, Hai Li, Ulf Schlichtmann, Massimo Alioto
Herausgeber (Verlag)IEEE Computer Society
Seiten243-248
Seitenumfang6
ISBN (elektronisch)9781538640333
DOIs
PublikationsstatusVeröffentlicht - 18 Dez. 2017
Veranstaltung30th IEEE International System on Chip Conference, SOCC 2017 - Munich, Deutschland
Dauer: 5 Sept. 20178 Sept. 2017

Publikationsreihe

NameInternational System on Chip Conference
Band2017-September
ISSN (Print)2164-1676
ISSN (elektronisch)2164-1706

Konferenz

Konferenz30th IEEE International System on Chip Conference, SOCC 2017
Land/GebietDeutschland
OrtMunich
Zeitraum5/09/178/09/17

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