Application-aware cross-layer reliability analysis and optimization

The increasing error susceptibility of semiconductor devices has put reliability in the focus of modern design methodologies. Low-level techniques alone cannot economically tackle this problem. Instead, counter measures on all system layers from device and circuit up to the application are required. As these counter measures are not for free, orchestrating them across different layers to achieve optimum trade-offs for the application wrt. reliability but also cost, timeliness, or energy consumption becomes a challenge. This typically requires a combination of analysis techniques to quantify the achieved reliability and optimization techniques that search for the best combination of counter measures. This work presents five recent approaches for application-aware cross-layer reliability optimization from within the embedded domain. Moreover, the Resilience Articulation Point (RAP) as a concept cooperatively developed to model errors across different layers is discussed. The developed approaches are showcased via applications, ranging from MIMO systems to distributed embedded control applications.