Application-aware aging analysis and mitigation for SRAM Design-for-Relability

Most embedded systems integrate several on-chip Static Random Access Memories (SRAMs). These SRAMs are increasingly susceptible to reliability threats such as Bias Temperature Instability (BTI) due to the continuous trend of technology shrinking. BTI leads to a significant performance degradation, especially in the Sense Amplifiers (SAs) of SRAMs, where failures are fatal, since the data of a whole column is destroyed. In this paper we present a new workload-aware aging analysis for On-Chip SRAMs. The method incorporates the workload of embedded applications while considering aging in the complete read-path and its control signals. According to this workload, we predict the performance degradation in the memory and its end of lifetime. Furthermore, we present the Mitigation of AGIng Circuitry (MAGIC), a low-cost circuitry to effectively mitigate aging in SAs by wear-leveling. We show that SRAM cell and SA aging have a significant contribution to the overall degradation of the read-path while aging in the SA's control signals counter-intuitively leads to minor performance improvements. The proposed mitigation scheme MAGIC can mitigate the degradation in the read-path up to ∼26% while introducing minimal area/performance overhead. Our application-aware end-of-life analysis shows that this translates into 3x longer lifetime.