An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

This article presents an open-source framework for emulating mixed-signal chip designs on a field-programmable gate array (FPGA). It includes a Python-based synthesizable model generator for mixed-signal blocks (msdsl), a fixed-point and floating-point synthesizable SystemVerilog library for representing real numbers (svreal), and a Python-based tool that generates emulator control infrastructure and automates the FPGA build process (anasymod). The framework includes features for efficiently modeling analog dynamics, nonlinearity, and noise, often making use of compile-Time caching to reduce the required computational resources of the FPGA. We demonstrate the framework's generality by discussing three applications: 1) a high-speed link receiver (DragonPHY); 2) a firmware-controlled flyback converter; and 3) an NFC-powered chip. Our framework makes it easy to emulate these systems, while providing runtimes 2-3 orders of magnitude faster than CPU simulations with real-number functional models.