TY - GEN
T1 - An Automated and Effective Approach for SBST Generation Targeting RISC-V CPUs
AU - Kaja, Endri
AU - Gerlin, Nicolas
AU - Halabi, Jad Al
AU - Tahiraga, Ares
AU - Prebeck, Sebastian
AU - Stoffel, Dominik
AU - Kunz, Wolfgang
AU - Ecker, Wolfgang
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - The trend toward scaling and more complex fabrication techniques in digital circuit design often leads to numerous faults within Integrated Circuits (ICs). To address these vulnerabilities, various Design-for-Test (DFT) techniques have been developed for thorough testing during IC manufacturing. However, integrating these DFT infrastructures introduces significant overhead in both area and performance. To overcome these challenges, especially for testing processor cores, Software-Based Self Test (SBST) has emerged as a promising alternative. This paper proposes a novel, automated, and efficient approach for generating SBST tailored for RISC-V processor cores. By combining formal verification with fault simulation, the number of required assertions is reduced by eliminating faults detected by existing test patterns. In addition to SBST generation, our approach introduces a novel Program Flow Checking (PFC) technique, ensuring adherence to ISO 26262 standards and providing a high Fault Detection Rate (FDR). Experimental results show that various RISC-V processor components achieve Fault Coverage (FC) greater than 91%, with the PFC providing a 100% FDR for most components. The methodology is fully automated, utilizing Model-Driven Architecture (MDA) principles.
AB - The trend toward scaling and more complex fabrication techniques in digital circuit design often leads to numerous faults within Integrated Circuits (ICs). To address these vulnerabilities, various Design-for-Test (DFT) techniques have been developed for thorough testing during IC manufacturing. However, integrating these DFT infrastructures introduces significant overhead in both area and performance. To overcome these challenges, especially for testing processor cores, Software-Based Self Test (SBST) has emerged as a promising alternative. This paper proposes a novel, automated, and efficient approach for generating SBST tailored for RISC-V processor cores. By combining formal verification with fault simulation, the number of required assertions is reduced by eliminating faults detected by existing test patterns. In addition to SBST generation, our approach introduces a novel Program Flow Checking (PFC) technique, ensuring adherence to ISO 26262 standards and providing a high Fault Detection Rate (FDR). Experimental results show that various RISC-V processor components achieve Fault Coverage (FC) greater than 91%, with the PFC providing a 100% FDR for most components. The methodology is fully automated, utilizing Model-Driven Architecture (MDA) principles.
KW - Fault Simulation
KW - Model-Driven
KW - PFC
KW - RISC-V
KW - SBST
UR - http://www.scopus.com/inward/record.url?scp=85212424647&partnerID=8YFLogxK
U2 - 10.1109/DFT63277.2024.10753552
DO - 10.1109/DFT63277.2024.10753552
M3 - Conference contribution
AN - SCOPUS:85212424647
T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
BT - 37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024
Y2 - 8 October 2024 through 10 October 2024
ER -