An Automated and Effective Approach for SBST Generation Targeting RISC-V CPUs

Endri Kaja, Nicolas Gerlin, Jad Al Halabi, Ares Tahiraga, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

Abstract

The trend toward scaling and more complex fabrication techniques in digital circuit design often leads to numerous faults within Integrated Circuits (ICs). To address these vulnerabilities, various Design-for-Test (DFT) techniques have been developed for thorough testing during IC manufacturing. However, integrating these DFT infrastructures introduces significant overhead in both area and performance. To overcome these challenges, especially for testing processor cores, Software-Based Self Test (SBST) has emerged as a promising alternative. This paper proposes a novel, automated, and efficient approach for generating SBST tailored for RISC-V processor cores. By combining formal verification with fault simulation, the number of required assertions is reduced by eliminating faults detected by existing test patterns. In addition to SBST generation, our approach introduces a novel Program Flow Checking (PFC) technique, ensuring adherence to ISO 26262 standards and providing a high Fault Detection Rate (FDR). Experimental results show that various RISC-V processor components achieve Fault Coverage (FC) greater than 91%, with the PFC providing a 100% FDR for most components. The methodology is fully automated, utilizing Model-Driven Architecture (MDA) principles.

OriginalspracheEnglisch
Titel37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers Inc.
ISBN (elektronisch)9798350366884
DOIs
PublikationsstatusVeröffentlicht - 2024
Veranstaltung37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024 - Didcot, Großbritannien/Vereinigtes Königreich
Dauer: 8 Okt. 202410 Okt. 2024

Publikationsreihe

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
ISSN (Print)2576-1501
ISSN (elektronisch)2765-933X

Konferenz

Konferenz37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024
Land/GebietGroßbritannien/Vereinigtes Königreich
OrtDidcot
Zeitraum8/10/2410/10/24

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