An approach for mixed coarse-granular and fine-granular re-configurable architectures

R. Henftling, W. Ecker, A. Zinn, M. Zambaldi, M. Bauer

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

Abstract

This paper focuses on a mixed coarse-granular and fine-granular re-configurable architecture that is used to build hardware testbenches for the verification of ASICs or system-on-a-chip designs. Here, "coarse-granular" architecture refers to micro-sequencers, and 'fine-granular" architecture refers to FPGAs. Hardware testbenches are derived from behavioral testbenches and testcases, which are written as micro-sequences. While the part of a testbench that controls the execution of the testcases is mapped to the coarse-granular architecture, the part that is responsible for the low-level protocol operations is mapped to the fine-granular architecture. The testcases are compiled into the program memories of the coarse-granular architecture. The mixed-granularity re-configurable architecture reduces modeling- and configuration-time as compared to a pure fine-granular solution. But it keeps the advantage of flexibility.

OriginalspracheEnglisch
TitelProceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers Inc.
ISBN (elektronisch)0769519261, 9780769519265
DOIs
PublikationsstatusVeröffentlicht - 2003
Extern publiziertJa
VeranstaltungInternational Parallel and Distributed Processing Symposium, IPDPS 2003 - Nice, Frankreich
Dauer: 22 Apr. 200326 Apr. 2003

Publikationsreihe

NameProceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003

Konferenz

KonferenzInternational Parallel and Distributed Processing Symposium, IPDPS 2003
Land/GebietFrankreich
OrtNice
Zeitraum22/04/0326/04/03

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