TY - GEN
T1 - An approach for mixed coarse-granular and fine-granular re-configurable architectures
AU - Henftling, R.
AU - Ecker, W.
AU - Zinn, A.
AU - Zambaldi, M.
AU - Bauer, M.
N1 - Publisher Copyright:
© 2003 IEEE.
PY - 2003
Y1 - 2003
N2 - This paper focuses on a mixed coarse-granular and fine-granular re-configurable architecture that is used to build hardware testbenches for the verification of ASICs or system-on-a-chip designs. Here, "coarse-granular" architecture refers to micro-sequencers, and 'fine-granular" architecture refers to FPGAs. Hardware testbenches are derived from behavioral testbenches and testcases, which are written as micro-sequences. While the part of a testbench that controls the execution of the testcases is mapped to the coarse-granular architecture, the part that is responsible for the low-level protocol operations is mapped to the fine-granular architecture. The testcases are compiled into the program memories of the coarse-granular architecture. The mixed-granularity re-configurable architecture reduces modeling- and configuration-time as compared to a pure fine-granular solution. But it keeps the advantage of flexibility.
AB - This paper focuses on a mixed coarse-granular and fine-granular re-configurable architecture that is used to build hardware testbenches for the verification of ASICs or system-on-a-chip designs. Here, "coarse-granular" architecture refers to micro-sequencers, and 'fine-granular" architecture refers to FPGAs. Hardware testbenches are derived from behavioral testbenches and testcases, which are written as micro-sequences. While the part of a testbench that controls the execution of the testcases is mapped to the coarse-granular architecture, the part that is responsible for the low-level protocol operations is mapped to the fine-granular architecture. The testcases are compiled into the program memories of the coarse-granular architecture. The mixed-granularity re-configurable architecture reduces modeling- and configuration-time as compared to a pure fine-granular solution. But it keeps the advantage of flexibility.
UR - http://www.scopus.com/inward/record.url?scp=84947257808&partnerID=8YFLogxK
U2 - 10.1109/IPDPS.2003.1213346
DO - 10.1109/IPDPS.2003.1213346
M3 - Conference contribution
AN - SCOPUS:84947257808
T3 - Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003
BT - Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - International Parallel and Distributed Processing Symposium, IPDPS 2003
Y2 - 22 April 2003 through 26 April 2003
ER -