TY - GEN
T1 - An advancedTCA based data concentrator and event building architecture
AU - Mann, Alexander B.
AU - Konorov, Igor
AU - Goslich, Florian
AU - Paul, Stephan
PY - 2010
Y1 - 2010
N2 - To address the data rate requirements for upcoming experiments in high energy physics, we present a configurable architecture for data concentration and event building, based on the AdvancedTCA and MicroTCA standards. The core component is a μTCA based module which connects a Lattice ECP3 FPGA to up to 8 front panel fiber ports for data input from front-end electronics. In addition, the fiber ports can distribute synchronization clock and configuration information from a central time distribution system. To buffer the incoming data, the module provides up to 2 soDIMM sockets for standard DDR3 memory modules. With different firmware functionality, the buffer module can then interface to a μTCA shelf backplane via e.g. PCI Express. To allow event building for more than 8 input links, 4 buffer modules can be combined on an ATCA carrier card, which connects to the high speed links on the μTCA connector. The connections between the 4 μTCA cards and the ATCA backplane can then be configured dynamically by a passive crosspoint switch on the ATCA carrier card. Thus, multiple event building topologies can be configured on the carrier card and within the full ATCA shelf to adapt to different system sizes and communication patterns.
AB - To address the data rate requirements for upcoming experiments in high energy physics, we present a configurable architecture for data concentration and event building, based on the AdvancedTCA and MicroTCA standards. The core component is a μTCA based module which connects a Lattice ECP3 FPGA to up to 8 front panel fiber ports for data input from front-end electronics. In addition, the fiber ports can distribute synchronization clock and configuration information from a central time distribution system. To buffer the incoming data, the module provides up to 2 soDIMM sockets for standard DDR3 memory modules. With different firmware functionality, the buffer module can then interface to a μTCA shelf backplane via e.g. PCI Express. To allow event building for more than 8 input links, 4 buffer modules can be combined on an ATCA carrier card, which connects to the high speed links on the μTCA connector. The connections between the 4 μTCA cards and the ATCA backplane can then be configured dynamically by a passive crosspoint switch on the ATCA carrier card. Thus, multiple event building topologies can be configured on the carrier card and within the full ATCA shelf to adapt to different system sizes and communication patterns.
UR - http://www.scopus.com/inward/record.url?scp=79955987136&partnerID=8YFLogxK
U2 - 10.1109/RTC.2010.5750387
DO - 10.1109/RTC.2010.5750387
M3 - Conference contribution
AN - SCOPUS:79955987136
SN - 9781424471096
T3 - Conference Record - 2010 17th IEEE-NPSS Real Time Conference, RT10
BT - Conference Record - 2010 17th IEEE-NPSS Real Time Conference, RT10
T2 - 2010 17th IEEE-NPSS Real Time Conference, RT10
Y2 - 24 May 2010 through 28 May 2010
ER -