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Algorithms for synthesizing priorities in component-based systems

  • Chih Hong Cheng
  • , Saddek Bensalem
  • , Yu Fang Chen
  • , Rongjie Yan
  • , Barbara Jobstmann
  • , Harald Ruess
  • , Christian Buckl
  • , Alois Knoll
  • Technische Universität München
  • UJF-Grenoble 1, CNRS VERIMAG UMR 5104
  • Academia Sinica, Institute of Information Science
  • ISCAS
  • Fortiss GmbH

Publikation: Beitrag in Buch/Bericht/Konferenzband › Konferenzbeitrag › Begutachtung

7 Zitate (Scopus)

Abstract

We present algorithms to synthesize component-based systems that are safe and deadlock-free using priorities, which define stateless-precedence between enabled actions. Our core method combines the concept of fault- localization (using safety-game) and fault-repair (using SAT for conflict resolution). For complex systems, we propose three complementary methods as preprocessing steps for priority synthesis, namely (a) data abstraction to reduce component complexities, (b) alphabet abstraction and #-deadlock to ignore components, and (c) automated assumption learning for compositional priority synthesis.

OriginalspracheEnglisch
TitelAutomated Technology for Verification and Analysis - 9th International Symposium, ATVA 2011, Proceedings
Seiten150-167
Seitenumfang18
DOIs
PublikationsstatusVeröffentlicht - 2011
Veranstaltung9th International Symposium on Automated Technology for Verification and Analysis, ATVA 2011 - Taipei, Taiwan
Dauer: 11 Okt. 2011 → 14 Okt. 2011

Publikationsreihe

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Band6996 LNCS
ISSN (Print)0302-9743
ISSN (elektronisch)1611-3349

Konferenz

Konferenz9th International Symposium on Automated Technology for Verification and Analysis, ATVA 2011
Land/GebietTaiwan
OrtTaipei
Zeitraum11/10/11 → 14/10/11

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