TY - GEN
T1 - A transaction-oriented UVM-based library for verification of analog behavior
AU - Rath, Alexander W.
AU - Esen, Volkan
AU - Ecker, Wolfgang
PY - 2014
Y1 - 2014
N2 - The Universal Verification Methodology (UVM) has become a de facto standard in today's functional verification of digital designs. However, it is rarely used for the verification of Designs Under Test containing Real Number Models. This paper presents a new technique using UVM that can be used in order to compare models of analog circuitry on different levels of abstraction. It makes use of statistic metrics. The presented technique enables us to ensure that Real Number Models used in chip projects match the transistor level circuitry during the whole life cycle of the project.
AB - The Universal Verification Methodology (UVM) has become a de facto standard in today's functional verification of digital designs. However, it is rarely used for the verification of Designs Under Test containing Real Number Models. This paper presents a new technique using UVM that can be used in order to compare models of analog circuitry on different levels of abstraction. It makes use of statistic metrics. The presented technique enables us to ensure that Real Number Models used in chip projects match the transistor level circuitry during the whole life cycle of the project.
UR - http://www.scopus.com/inward/record.url?scp=84897861781&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2014.6742989
DO - 10.1109/ASPDAC.2014.6742989
M3 - Conference contribution
AN - SCOPUS:84897861781
SN - 9781479928163
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 806
EP - 811
BT - 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings
T2 - 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
Y2 - 20 January 2014 through 23 January 2014
ER -