A transaction-oriented UVM-based library for verification of analog behavior

Alexander W. Rath, Volkan Esen, Wolfgang Ecker

Publikation: Beitrag in Buch/Bericht/KonferenzbandKonferenzbeitragBegutachtung

9 Zitate (Scopus)

Abstract

The Universal Verification Methodology (UVM) has become a de facto standard in today's functional verification of digital designs. However, it is rarely used for the verification of Designs Under Test containing Real Number Models. This paper presents a new technique using UVM that can be used in order to compare models of analog circuitry on different levels of abstraction. It makes use of statistic metrics. The presented technique enables us to ensure that Real Number Models used in chip projects match the transistor level circuitry during the whole life cycle of the project.

OriginalspracheEnglisch
Titel2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings
Seiten806-811
Seitenumfang6
DOIs
PublikationsstatusVeröffentlicht - 2014
Extern publiziertJa
Veranstaltung2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Suntec, Singapur
Dauer: 20 Jan. 201423 Jan. 2014

Publikationsreihe

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Konferenz

Konferenz2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
Land/GebietSingapur
OrtSuntec
Zeitraum20/01/1423/01/14

Fingerprint

Untersuchen Sie die Forschungsthemen von „A transaction-oriented UVM-based library for verification of analog behavior“. Zusammen bilden sie einen einzigartigen Fingerprint.

Dieses zitieren