A novel analysis technique of power supply noise (PSN) for cmos circuits using external current sensor with automatic test equipment

The major drawback of PSN simulation approach is the fact that it is guaranteed only for a particular set of simulated tests, as the actual PSN value can change if we use a different set of tests. On the other hand, conventional ATE can not detect a dynamic peak current or spike with a very high resolution due to the constraint of slaw measurement sampling frequency. Thereby, it is very difficult to analyze design weaknesses due to PSN issue by ATE as well as by simulation approach. In this paper, we proposed to capture the high-resolution dynamic peak current using a high-speed external current sensor and a digital oscilloscope. The oscilloscope is controlled by ATE via standard IEEE-488 GPIB, such that a high resolution of dynamic current profiles with respect to different specific test sequences can be analyzed in detail automatically. Furthermore, we use computational intelligence techniques (CIT) such as neural network and genetic algorithm with ATE to improve the test with respect to the detected (full-chip) dynamic peak current. Our experimental results demonstrate the improvement of the (full-chip) dynamic peak current acquisition, and better worst case tests can be detected practically with this approach.